The disclosure relates generally to methods and apparatus for voltage level shifting.
In integrated circuits having an input/output (I/O) circuit, because internal core logic can operate in an internal core logic voltage domain that is different from an I/O voltage domain in which the I/O circuit operates, voltage level shifting is required to propagate signals from the internal core logic to the I/O circuit. In addition, for high-speed synchronous I/O circuits, the output data signal is typically required to be synchronized with a clock through a flip-flop or a latch prior to being sent out, to clean up signal timing jitter from the upstream data path.
One technique for performing the voltage domain level shifting and the output data signal synchronization is to synchronize the data signal in the lower voltage domain (e.g., an internal core logic voltage domain) with a flip-flop or a latch, then shift the voltage level of the synchronized output data signal to the higher voltage domain (e.g., an I/O voltage domain) so that the signal can be driven out through an I/O buffer. Another technique for performing the voltage domain level shifting and the output data signal synchronization is to shift the voltage level of both the output data signal and the clock signal from the internal core logic voltage domain to the I/O voltage domain, then synchronize the level shifted output data signal with the level shifted clock signal in the I/O voltage domain with a flip-flop or a latch operating on the I/O power rail. Both techniques typically require two separate and sequential operations and corresponding circuits, for example, a synchronization operation followed by a level shifting operating or vice versa. In other words, an asynchronous level shifting scheme is employed by the above-mentioned techniques, which typically adds jitter to the resulting output data signal.
In addition, existing level shifting circuits may only rely on pull-down voltage signals generated by NMOS transistors to flip the logic polarity of the differential output data signals. As such, the duty cycle of the output signal may be distorted by the varying of the internal core logic voltage, especially when the internal core logic voltage is down to near the minimum common-collector voltage (VCCmin) of the technology process.
Accordingly, there exists a need for improved methods and apparatus for voltage level shifting.